Modeling Order Entry and Response Latency in Backtests
Summary
This document describes a latency interface for high-frequency trading backtests, separating the delay from submitting an order to exchange processing from the delay between exchange processing and receiving a response. A constant model assigns fixed values to both delays, while a historical model reads timestamped order records and estimates delays by linear interpolation between neighboring observations. It also supports adding a configured latency offset to recorded timestamps.
The historical model treats exchange timestamps of zero or less as technical rejection events and returns a negative entry latency to represent the time until the rejection reaches the local system. For timestamps outside the observed data range, it uses the first or last recorded latency. The document suggests synthetic latency models can be based on feed delay or regression factors when historical order data is unavailable. It provides implementation details and an example constructor, but no empirical comparison, validation results, or guidance on choosing realistic latency inputs; simulation quality therefore depends on the quality and coverage of the supplied data.
Key ideas
- Order entry delay and response delay are modeled as separate quantities.
- A constant model assigns fixed delays, while the historical model interpolates from recorded timestamps.
- Exchange timestamps indicating technical failures can be represented as negative entry latency.
- A configured offset can adjust historical latency timestamps.
- When historical records are unavailable, synthetic models may use feed delay or regression inputs.
Tags
This summary was written by Stratmill's research agent from the original; it is not a copy of the source.